

#ifndef _DT_BINDINGS_CLK_SUN8I_V3S_H_
#define _DT_BINDINGS_CLK_SUN8I_V3S_H_

#define CLK_CPU			14

#define CLK_BUS_CE		20
#define CLK_BUS_DMA		21
#define CLK_BUS_MMC0		22
#define CLK_BUS_MMC1		23
#define CLK_BUS_MMC2		24
#define CLK_BUS_DRAM		25
#define CLK_BUS_EMAC		26
#define CLK_BUS_HSTIMER		27
#define CLK_BUS_SPI0		28
#define CLK_BUS_OTG		29
#define CLK_BUS_EHCI0		30
#define CLK_BUS_OHCI0		31
#define CLK_BUS_VE		32
#define CLK_BUS_TCON0		33
#define CLK_BUS_CSI		34
#define CLK_BUS_DE		35
#define CLK_BUS_CODEC		36
#define CLK_BUS_PIO		37
#define CLK_BUS_I2C0		38
#define CLK_BUS_I2C1		39
#define CLK_BUS_UART0		40
#define CLK_BUS_UART1		41
#define CLK_BUS_UART2		42
#define CLK_BUS_EPHY		43
#define CLK_BUS_DBG		44

#define CLK_MMC0		45
#define CLK_MMC0_SAMPLE		46
#define CLK_MMC0_OUTPUT		47
#define CLK_MMC1		48
#define CLK_MMC1_SAMPLE		49
#define CLK_MMC1_OUTPUT		50
#define CLK_MMC2		51
#define CLK_MMC2_SAMPLE		52
#define CLK_MMC2_OUTPUT		53
#define CLK_CE			54
#define CLK_SPI0		55
#define CLK_USB_PHY0		56
#define CLK_USB_OHCI0		57

#define CLK_DRAM_VE		59
#define CLK_DRAM_CSI		60
#define CLK_DRAM_EHCI		61
#define CLK_DRAM_OHCI		62
#define CLK_DE			63
#define CLK_TCON0		64
#define CLK_CSI_MISC		65
#define CLK_CSI0_MCLK		66
#define CLK_CSI1_SCLK		67
#define CLK_CSI1_MCLK		68
#define CLK_VE			69
#define CLK_AC_DIG		70
#define CLK_AVS			71

#define CLK_MIPI_CSI		73


#define CLK_BUS_I2S0		75
#define CLK_I2S0		76

#endif 
