/* SPDX-License-Identifier: GPL-2.0 */


#ifndef DT_BINDINGS_CLOCK_TEGRA234_CLOCK_H
#define DT_BINDINGS_CLOCK_TEGRA234_CLOCK_H



#define TEGRA234_CLK_AHUB			4U

#define TEGRA234_CLK_APB2APE			5U

#define TEGRA234_CLK_APE			6U

#define TEGRA234_CLK_AUD_MCLK			7U

#define TEGRA234_CLK_DMIC1			15U

#define TEGRA234_CLK_DMIC2			16U

#define TEGRA234_CLK_DMIC3			17U

#define TEGRA234_CLK_DMIC4			18U

#define TEGRA234_CLK_DSPK1			29U

#define TEGRA234_CLK_DSPK2			30U

#define TEGRA234_CLK_EMC			31U

#define TEGRA234_CLK_HOST1X                     46U

#define TEGRA234_CLK_FUSE			40U

#define TEGRA234_CLK_I2C1			48U

#define TEGRA234_CLK_I2C2			49U

#define TEGRA234_CLK_I2C3			50U

#define TEGRA234_CLK_I2C4			51U

#define TEGRA234_CLK_I2C6			52U

#define TEGRA234_CLK_I2C7			53U

#define TEGRA234_CLK_I2C8			54U

#define TEGRA234_CLK_I2C9			55U

#define TEGRA234_CLK_I2S1			56U

#define TEGRA234_CLK_I2S1_SYNC_INPUT		57U

#define TEGRA234_CLK_I2S2			58U

#define TEGRA234_CLK_I2S2_SYNC_INPUT		59U

#define TEGRA234_CLK_I2S3			60U

#define TEGRA234_CLK_I2S3_SYNC_INPUT		61U

#define TEGRA234_CLK_I2S4			62U

#define TEGRA234_CLK_I2S4_SYNC_INPUT		63U

#define TEGRA234_CLK_I2S5			64U

#define TEGRA234_CLK_I2S5_SYNC_INPUT		65U

#define TEGRA234_CLK_I2S6			66U

#define TEGRA234_CLK_I2S6_SYNC_INPUT		67U

#define TEGRA234_CLK_PLLA			93U

#define TEGRA234_CLK_PLLP_OUT0			102U

#define TEGRA234_CLK_PLLA_OUT0			104U

#define TEGRA234_CLK_PWM1			105U

#define TEGRA234_CLK_PWM2			106U

#define TEGRA234_CLK_PWM3			107U

#define TEGRA234_CLK_PWM4			108U

#define TEGRA234_CLK_PWM5			109U

#define TEGRA234_CLK_PWM6			110U

#define TEGRA234_CLK_PWM7			111U

#define TEGRA234_CLK_PWM8			112U

#define TEGRA234_CLK_SDMMC4			123U

#define TEGRA234_CLK_SYNC_DMIC1			139U

#define TEGRA234_CLK_SYNC_DMIC2			140U

#define TEGRA234_CLK_SYNC_DMIC3			141U

#define TEGRA234_CLK_SYNC_DMIC4			142U

#define TEGRA234_CLK_SYNC_DSPK1			143U

#define TEGRA234_CLK_SYNC_DSPK2			144U

#define TEGRA234_CLK_SYNC_I2S1			145U

#define TEGRA234_CLK_SYNC_I2S2			146U

#define TEGRA234_CLK_SYNC_I2S3			147U

#define TEGRA234_CLK_SYNC_I2S4			148U

#define TEGRA234_CLK_SYNC_I2S5			149U

#define TEGRA234_CLK_SYNC_I2S6			150U

#define TEGRA234_CLK_UARTA			155U

#define TEGRA234_CLK_PEX1_C6_CORE		161U

#define TEGRA234_CLK_VIC                        167U

#define TEGRA234_CLK_PEX2_C7_CORE		171U

#define TEGRA234_CLK_PEX2_C8_CORE		172U

#define TEGRA234_CLK_PEX2_C9_CORE		173U

#define TEGRA234_CLK_PEX2_C10_CORE		187U

#define TEGRA234_CLK_QSPI0_2X_PM		192U

#define TEGRA234_CLK_QSPI1_2X_PM		193U

#define TEGRA234_CLK_QSPI0_PM			194U

#define TEGRA234_CLK_QSPI1_PM			195U

#define TEGRA234_CLK_SDMMC_LEGACY_TM		219U

#define TEGRA234_CLK_PEX0_C0_CORE		220U

#define TEGRA234_CLK_PEX0_C1_CORE		221U

#define TEGRA234_CLK_PEX0_C2_CORE		222U

#define TEGRA234_CLK_PEX0_C3_CORE		223U

#define TEGRA234_CLK_PEX0_C4_CORE		224U

#define TEGRA234_CLK_PEX1_C5_CORE		225U

#define TEGRA234_CLK_PLLC4			237U

#define TEGRA234_CLK_MGBE0_RX_INPUT		248U

#define TEGRA234_CLK_MGBE1_RX_INPUT		249U

#define TEGRA234_CLK_MGBE2_RX_INPUT		250U

#define TEGRA234_CLK_MGBE3_RX_INPUT		251U

#define TEGRA234_CLK_CLK_32K			289U

#define TEGRA234_CLK_MGBE0_RX_INPUT_M		357U

#define TEGRA234_CLK_MGBE1_RX_INPUT_M		358U

#define TEGRA234_CLK_MGBE2_RX_INPUT_M		359U

#define TEGRA234_CLK_MGBE3_RX_INPUT_M		360U

#define TEGRA234_CLK_MGBE0_RX_PCS_M		361U

#define TEGRA234_CLK_MGBE1_RX_PCS_M		362U

#define TEGRA234_CLK_MGBE2_RX_PCS_M		363U

#define TEGRA234_CLK_MGBE3_RX_PCS_M		364U

#define TEGRA234_CLK_MGBE0_RX_PCS_INPUT		369U

#define TEGRA234_CLK_MGBE1_RX_PCS_INPUT		370U

#define TEGRA234_CLK_MGBE2_RX_PCS_INPUT		371U

#define TEGRA234_CLK_MGBE3_RX_PCS_INPUT		372U

#define TEGRA234_CLK_MGBE0_RX_PCS		373U

#define TEGRA234_CLK_MGBE0_TX			374U

#define TEGRA234_CLK_MGBE0_TX_PCS		375U

#define TEGRA234_CLK_MGBE0_MAC_DIVIDER		376U

#define TEGRA234_CLK_MGBE0_MAC			377U

#define TEGRA234_CLK_MGBE0_MACSEC		378U

#define TEGRA234_CLK_MGBE0_EEE_PCS		379U

#define TEGRA234_CLK_MGBE0_APP			380U

#define TEGRA234_CLK_MGBE0_PTP_REF		381U

#define TEGRA234_CLK_MGBE1_RX_PCS		382U

#define TEGRA234_CLK_MGBE1_TX			383U

#define TEGRA234_CLK_MGBE1_TX_PCS		384U

#define TEGRA234_CLK_MGBE1_MAC_DIVIDER		385U

#define TEGRA234_CLK_MGBE1_MAC			386U

#define TEGRA234_CLK_MGBE1_EEE_PCS		388U

#define TEGRA234_CLK_MGBE1_APP			389U

#define TEGRA234_CLK_MGBE1_PTP_REF		390U

#define TEGRA234_CLK_MGBE2_RX_PCS		391U

#define TEGRA234_CLK_MGBE2_TX			392U

#define TEGRA234_CLK_MGBE2_TX_PCS		393U

#define TEGRA234_CLK_MGBE2_MAC_DIVIDER		394U

#define TEGRA234_CLK_MGBE2_MAC			395U

#define TEGRA234_CLK_MGBE2_EEE_PCS		397U

#define TEGRA234_CLK_MGBE2_APP			398U

#define TEGRA234_CLK_MGBE2_PTP_REF		399U

#define TEGRA234_CLK_MGBE3_RX_PCS		400U

#define TEGRA234_CLK_MGBE3_TX			401U

#define TEGRA234_CLK_MGBE3_TX_PCS		402U

#define TEGRA234_CLK_MGBE3_MAC_DIVIDER		403U

#define TEGRA234_CLK_MGBE3_MAC			404U

#define TEGRA234_CLK_MGBE3_MACSEC		405U

#define TEGRA234_CLK_MGBE3_EEE_PCS		406U

#define TEGRA234_CLK_MGBE3_APP			407U

#define TEGRA234_CLK_MGBE3_PTP_REF		408U

#define TEGRA234_CLK_AZA_2XBIT			457U

#define TEGRA234_CLK_AZA_BIT			458U

#endif
